reg1010.h

/*****************************************************************************
 *                                                                           *
 *        **********                                                         *
 *       ************                                                        *
 *      ***        ***                                                       *
 *      ***   +++   ***                                                      *
 *      ***   + +   ***                                                      *
 *      ***   +                            CHIPCON CC1010                    *
 *      ***   + +   ***           HARDWARE REGISTER DEFINITION FILE          *
 *      ***   +++   ***                                                      *
 *      ***       ***                                                        *
 *       ***********                                                         *
 *        *********                                                          *
 *                                                                           *
 *****************************************************************************
 * The Chipcon Hardware Register definition file is a header file defining   *
 * mnemonic names for CC1010 SFR registers, individually addressable SFR     *
 * bits and interrupt service routine addresses.                             *
 *****************************************************************************
 * Author:              ROH                                                  *
 *****************************************************************************
 * Revision history:                                                         *
 * 1.0  2002/04/01      First Public Release                                 *
 *                                                                           *
 * $Log: Reg1010.h,v $
 * Revision 1.1  2002/10/14 11:49:08  tos
 * Initial version in CVS.
 *
 *                                                                           *
 ****************************************************************************/
#ifndef WIN32
#ifndef REG1010_H

#define REG1010_H       // Only include this header file once

/* Real clock Timer Control */
sfr at 0xED RTCON;

/*A/D*/
sfr at 0x93 ADCON;
sfr at 0x94 ADDATL;
sfr at 0x95 ADDATH;
sfr at 0x96 ADCON2;
sfr at 0x97 ADTRH;


/* Chip version */
sfr at 0x9F CHVER;

/* Triac */
sfr at 0x9A TRICON;
sfr at 0x9B TRI3;
sfr at 0x9C TRI2; 
sfr at 0x9D TRI1;
sfr at 0x9E TRI0;

/* Flash write */
sfr at 0xAE FLADR;
sfr at 0xAF FLCON;
sfr at 0xDD FLTIM;

/* SPI */
sfr at 0xA1 SPCR;
sfr at 0xA2 SPDR;
sfr at 0xA3 SPSR;

/* Timer 2 / 3 */
sfr at 0xA9 TCON2;
sfr at 0xAA T2PRE;
sfr at 0xAB T3PRE;
sfr at 0xAC T2;
sfr at 0xAD T3;

  /*  Encryption / decryption initialisation vector */
sfr at 0xB4 CRPINI0;
sfr at 0xB5 CRPINI1;
sfr at 0xB6 CRPINI2;
sfr at 0xB7 CRPINI3;
sfr at 0xBC CRPINI4;
sfr at 0xBD CRPINI5;
sfr at 0xBE CRPINI6;
sfr at 0xBF CRPINI7;

/*    -- RF Control */
sfr at 0xC2 RFCON;

/* -- Encryption / decryption initialisation vector */
sfr at 0xC3 CRPCON;
sfr at 0xC4 CRPKEY;
sfr at 0xC5 CRPDAT;
sfr at 0xC6 CRPCNT;

/* -- Main config register */
sfr at 0xC8 RFMAIN;

/* -- RF Data input / output */
sfr at 0xC9 RFBUF;

/* -- Frequency multiply registers */
sfr at 0xCA FREQ_0A;
sfr at 0xCB FREQ_1A;
sfr at 0xCC FREQ_2A;
sfr at 0xCD FREQ_0B;
sfr at 0xCE FREQ_1B;
sfr at 0xCF FREQ_2B;

/* -- Power control */
sfr at 0xD1 X32CON;

/* -- Watchdog */
sfr at 0xD2 WDT;

/* -- Preamble */
sfr at 0xD3 PDET;
sfr at 0xd4 BSYNC;

/* -- Modulator / Demodulator conntrol */
sfr at 0xD9 MODEM2;
sfr at 0xDA MODEM1;
sfr at 0xDB MODEM0;

/* -- Matching of cap array */
sfr at 0xDC MATCH;

/* -- Control signals */
sfr at 0xE1 CURRENT;
sfr at 0xE2 PA_POW;
sfr at 0xE3 PLL;
sfr at 0xE4 LOCK;
sfr at 0xE5 CAL;
sfr at 0xEE FREND;

/* -- Frequency shaping delay */
sfr at 0xE9 FSDELAY;

/* -- Frequency separation registers */
sfr at 0xEA FSEP0;
sfr at 0xEB FSEP1;

/* -- Frequency synthesiser control */
sfr at 0xEC FSCTRL;

/* -- Frequency shaping */
sfr at 0xF1 FSHAPE7;
sfr at 0xF2 FSHAPE6;
sfr at 0xF3 FSHAPE5;
sfr at 0xF4 FSHAPE4;
sfr at 0xF5 FSHAPE3;
sfr at 0xF6 FSHAPE2;
sfr at 0xF7 FSHAPE1;

/* -- Test and status registers */
sfr at 0xF9 TEST0;
sfr at 0xFA TEST1;
sfr at 0xFB TEST2;
sfr at 0xFC TEST3;
sfr at 0xFD TEST4;
sfr at 0xFE TEST5;
sfr at 0xFF TEST6;
sfr at 0xEF TESTMUX;

/* The rest! */
sfr at 0xE0 ACC;

/*Ports*/
sfr at 0x80 P0; /*Only P0.3 to P0.3 exists*/
sfr at 0x90 P1; /*P1.0 to P1.7*/
sfr at 0xA0 P2;
sfr at 0xB0 P3; /*Only P3.0 to P3.5 exists*/

sfr at 0xA4 P0DIR;
sfr at 0xA5 P1DIR;
sfr at 0xA6 P2DIR;
sfr at 0xA7 P3DIR;

sfr at 0x81 SP;

sfr at 0x82 DPL0;
sfr at 0x83 DPH0;

sfr at 0x84 DPL1;
sfr at 0x85 DPH1;

sfr at 0x86 DPS;

sfr at 0x87 PCON;
sfr at 0x88 TCON;
sfr at 0x89 TMOD;
sfr at 0x8A TL0;
sfr at 0x8B TL1;
sfr at 0x8C TH0;
sfr at 0x8D TH1;
sfr at 0x8E CKCON;

sfr at 0x91 EXIF;
sfr at 0x92 MPAGE;
sfr at 0x98 SCON0;
sfr at 0x99 SBUF0;
sfr at 0xA8 IE;
sfr at 0xB8 IP;


sfr at 0xC0 SCON1;
sfr at 0xC1 SBUF1;

sfr at 0xD0 PSW;

sfr at 0xD8 EICON;
sfr at 0xE8 EIE;
sfr at 0xF0 B;
sfr at 0xF8 EIP;

sfr at 0xC7 RANCON;
sfr at 0xB9 RDATA;
sfr at 0xBA RADRL;
sfr at 0xBB RADRH;

sfr at 0xE6 PRESCALER;
sfr at 0xE7 RESERVED;


/******  BIT accessible Registers ******/
/*P0*/
sbit at 0x80^0 P0_0;
sbit at 0x80^1 P0_1;
sbit at 0x80^2 P0_2;
sbit at 0x80^3 P0_3;

sbit at 0x80^2 MI;
sbit at 0x80^1 MO;
sbit at 0x80^0 SCK;

/*P1*/
sbit at 0x90^0 P1_0;
sbit at 0x90^1 P1_1;
sbit at 0x90^2 P1_2;
sbit at 0x90^3 P1_3;
sbit at 0x90^4 P1_4;
sbit at 0x90^5 P1_5;
sbit at 0x90^6 P1_6;
sbit at 0x90^7 P1_7;


/*P2*/
sbit at 0xA0^0 P2_0;
sbit at 0xA0^1 P2_1;
sbit at 0xA0^2 P2_2;
sbit at 0xA0^3 P2_3;
sbit at 0xA0^4 P2_4;
sbit at 0xA0^5 P2_5;
sbit at 0xA0^6 P2_6;
sbit at 0xA0^7 P2_7;

sbit at 0xA0^0 RXD1;
sbit at 0xA0^1 TXD1;
sbit at 0xA0^2 ZEROX;
sbit at 0xA0^3 TRIAC;

/*P3 */
sbit at 0xB0^0 P3_0;
sbit at 0xB0^1 P3_1;
sbit at 0xB0^2 P3_2;
sbit at 0xB0^3 P3_3;
sbit at 0xB0^4 P3_4;
sbit at 0xB0^5 P3_5;

sbit at 0xB0^0 RXD0;
sbit at 0xB0^1 TXD0;
sbit at 0xB0^2 INT0_N;
sbit at 0xB0^3 INT1_N;
sbit at 0xB0^4 T0;
sbit at 0xB0^5 T1;


/*  TCON  */
sbit at 0x88^7 TF1;
sbit at 0x88^6 TR1;
sbit at 0x88^5 TF0;
sbit at 0x88^4 TR0;
sbit at 0x88^3 IE1;
sbit at 0x88^2 IT1;
sbit at 0x88^1 IE0;
sbit at 0x88^0 IT0;

/*  SCON0  */
sbit at 0x98^7 SM0_0; 
sbit at 0x98^6 SM1_0; 
sbit at 0x98^5 SM2_0; 
sbit at 0x98^4 REN_0; 
sbit at 0x98^3 TB8_0; 
sbit at 0x98^2 RB8_0; 
sbit at 0x98^1 TI_0; 
sbit at 0x98^0 RI_0; 

/*  SCON1  */
sbit at 0xC0^7 SM0_1; 
sbit at 0xC0^6 SM1_1; 
sbit at 0xC0^5 SM2_1; 
sbit at 0xC0^4 REN_1; 
sbit at 0xC0^3 TB8_1; 
sbit at 0xC0^2 RB8_1; 
sbit at 0xC0^1 TI_1; 
sbit at 0xC0^0 RI_1; 

/*IE*/
sbit at 0xA8^7 EA;
sbit at 0xA8^6 ES1;
sbit at 0xA8^4 ES0;
sbit at 0xA8^3 ET1;
sbit at 0xA8^2 EX1;
sbit at 0xA8^1 ET0;
sbit at 0xA8^0 EX0;

/*IP*/
sbit at 0xB8^6 PS1;
sbit at 0xB8^4 PS0;
sbit at 0xB8^3 PT1;
sbit at 0xB8^2 PX1;
sbit at 0xB8^1 PT0;
sbit at 0xB8^0 PX0;


/*RFMAIN*/
sbit at 0xC8^7 RXTX; /*RX/TX switch*/
sbit at 0xC8^6 F_REG; /*Select the freq registers A or B*/
sbit at 0xC8^5 RX_PD; /*Select Pwr down for LDA, Mixer, IF, Demulator, RX part of signal interface*/
sbit at 0xC8^4 TX_PD; /*Select Pwr down for TX part of signal interface and PA*/
sbit at 0xC8^3 FS_PD; /*Select Pwr down of freq syntesiser*/
sbit at 0xC8^2 CORE_PD; /*Power down main xtal osc core*/
sbit at 0xC8^1 BIAS_PD;  /* Power down bias current generator and xtal osc buffer*/


/*PSW*/
/*  PSW */
sbit at 0xD0^7 CY;
sbit at 0xD0^6 AC;
sbit at 0xD0^5 F0;
sbit at 0xD0^4 RS1;
sbit at 0xD0^3 RS0;
sbit at 0xD0^2 OV;
sbit at 0xD0^1 FL;
sbit at 0xD0^0 P;

/*EICON*/
sbit at 0xD8^7 SMOD1;
sbit at 0xD8^5 FDIE;
sbit at 0xD8^4 FDIF;
sbit at 0xD8^3 RTCIF;

/*ACC*/

/*EIE*/
sbit at 0xE8^4 RTCIE;
sbit at 0xE8^3 ET3;
sbit at 0xE8^2 ADIE;
sbit at 0xE8^1 ET2;
sbit at 0xE8^0 RFIE;

/*B*/


/*EIP*/
sbit at 0xF8^4 PRTC;
sbit at 0xF8^3 PT3;
sbit at 0xF8^2 PAD;
sbit at 0xF8^1 PT2;
sbit at 0xF8^0 PRF;


/****Common 8051 SFR registers not previously defined****/
/*  BYTE Register  */
sfr at 0x82 DPL;
sfr at 0x83 DPH;
sfr at 0x98 SCON;
sfr at 0x99 SBUF;

/*  BIT Register  */
/*  IE   */
sbit at 0xAC ES;

/*  IP   */ 
sbit at 0xBC PS;

/*  P3  */
sbit at 0xB3 INT1;
sbit at 0xB2 INT0;
sbit at 0xB1 TXD;
sbit at 0xB0 RXD;

/*  SCON  */
sbit at 0x9F SM0;
sbit at 0x9E SM1;
sbit at 0x9D SM2;
sbit at 0x9C REN;
sbit at 0x9B TB8;
sbit at 0x9A RB8;
sbit at 0x99 TI;
sbit at 0x98 RI;

// ************************* ISR vector addresses ****************************
// Usage example:
//      void my_serial_isr() interrupt INUM_UART0 {
//          ...
//      }

//INUM servicing FLASH DMA write finished / in-circuit debugger (opcode=0xA5)
#define INUM_FLASH      6

//ISR servicing external interrupt 0
#define INUM_INT0       0
#define INUM_EXTERNAL0  0

//ISR servicing timer 0
#define INUM_TIMER0     1

//ISR servicing external interrupt 1
#define INUM_INT1       2
#define INUM_EXTERNAL1  2

//ISR servicing timer 1
#define INUM_TIMER1     3

//ISR servicing serial port 0
#define INUM_SERIAL0    4
#define INUM_UART0      4
#define INUM_UART0_RX   40             // Can not be an ISR
#define INUM_UART0_TX   41             // Can not be an ISR

//ISR servicing serial port 1
#define INUM_SERIAL1    7
#define INUM_UART1      7
#define INUM_UART1_RX   70             // Can not be an ISR
#define INUM_UART1_TX   71             // Can not be an ISR

//ISR servicing RF receive/transmit
#define INUM_RF         8

//ISR servicing timer 2
#define INUM_TIMER2     9

//ISR servicing DES module / ADC 
#define INUM_DES_ADC    10
#define INUM_DES        100             // Can not be an ISR
#define INUM_ADC        101             // Can not be an ISR

//ISR servicing timer 3
#define INUM_TIMER3     11

//ISR servicing Realtime clock
#define INUM_RTC        12

#endif //REG1010_H
#endif /*If not WIN32*/

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